The present invention generally relates to technology for a semiconductor device, and more particularly, to a start-up circuit included a constant current circuit.
This application is a counterpart of Japanese patent application, Serial Number 317914/2000, filed Oct. 18, 2000, the subject matter of which is incorporated herein by reference.
A conventional semiconductor device is disclosed as shown in FIGS. 5-6. FIG. 5 is a circuit diagram showing the conventional semiconductor device. FIG. 6 is a chart showing a change of a power supply voltage level and a voltage level at a node N3.
The conventional semiconductor device comprises a node N1 being supplied with a power supply voltage VDD, a node N2 being supplied with a ground voltage GND, a resistor R1, a current mirror circuit 501, a current mirror circuit 502 and a start-up circuit 503. The current mirror circuit 501 comprises an input terminal 501I, an output terminal 501O, PMOS transistor (P-channel MOSFET) T1 and PMOS transistor T2. The gate electrodes of PMOS transistors T1 and T2 are connected to each other. The current mirror circuit 502 comprises an input terminal 502I, an output terminal 502O, NMOS transistor (N-channel MOSFET) T3 and NMOS transistor T4. The gate electrodes of NMOS transistors T3 and T4 are connected to each other. The resistor R1 has two terminals, one of which is connected to the current mirror circuit 502 and the other of which is connected to the node N2. The conventional start-up circuit 503 comprises a node N3, PMOS transistor T5, a resistor R2 and a capacitor C1. PMOS transistor T5 has a gate electrode connecting to the node N3, a source electrode connecting to the node N1 and a drain electrode connecting to an input terminal 502I of the current mirror circuit 502. PMOS transistor T5 is in an ON state when the gate electrode thereof has a second voltage. PMOS transistor T5 is in an OFF state when the gate electrode thereof has a first voltage. The resistor R2 has two terminals, one of which is connected to the node N1 and the other of which is connected to the node N3. The capacitor C1 has two terminals, one of which is connected to the node N3 and the other of which is connected to the node N2.
Next, the operation of the conventional semiconductor device will be described as follows.
When power turns on in the conventional semiconductor device, the voltage on the node N3 is the second voltage. At this time, the voltage on the gate electrode of PMOS transistor T5 also is the second voltage. A current path occurs between the source electrode and the drain electrode of PMOS transistor T5. Therefore, a current path occurs between the power supply voltage node VDD and the input terminal 502I through PMOS transistor T5. The voltage on the gate electrode of NMOS transistor T3 increases. A current path occurs between the input terminal 502I and the ground voltage GND. Since the gate electrodes of NMOS transistors T3 and T4 are connected to each other, the gate electrode of NMOS transistor T4 increases. A current path occurs between the output terminal 502O and the ground voltage GND. The voltage on the gate electrode PMOS transistor T1 decreases. A current path occurs between the power supply voltage VDD and the input terminal 501I. Therefore, a current path occurs between the power supply voltage VDD and the ground voltage GND through PMOS transistor T1 and NMOS transistor T4. Since the gate electrodes of PMOS transistors T1 and T2 are connected to each other, the gate electrode of PMOS transistor T2 decreases. A current path occurs between the power supply voltage VDD and the output terminal 501O. Therefore, a current path occurs between the power supply voltage VDD and the ground voltage GND through PMOS transistor T2 and NMOS transistor T3.
On the other hand, the voltage level on the node N3 gradually increases to the first voltage. PMOS transistor T5 goes into the OFF state. Therefore, a current path between the power supply voltage node VDD to the input terminal 502I through PMOS transistor T5 is cut off. However, the conventional semiconductor device operates stably, because current at the input terminals 501I and 502I has already begun flowing.
As shown in FIG. 6(A), when an increase (a solid line) in the power supply voltage VDD occurs faster than an increase (a dotted line) in the voltage on the node N3 (speed determined by a time constant of the resistor R2 and the capacitor C1), the potential difference occurs between the power supply voltage VDD (the source electrode of PMOS transistor T5) and the node N3 (the gate electrode of PMOS transistor T5). The potential difference lets the current path between the source and drain electrodes of PMOS transistor T5 occur.
However, as shown in FIG. 6(B), when an increase (a solid line) in the supply voltage VDD occurs slowly (in other words, when the voltage level of the power supply voltage VDD increases with an increase in the time constant), the potential difference which lets the current path between the source and drain electrodes of PMOS transistor T5 occur does not occur. Therefore, the conventional semiconductor device can not work. To solve the above problem, there is a measure which lets the resistance value of the resistor R2 be high and which lets the capacitance the capacitor C1 be large. At this time, to obtain a desired increase in speed of the power supply voltage VDD, which is 500 ms (microsecond), the semiconductor device must have the resistor R2, the resistor value of which is 5G xcexa9 (gigaohm) and the capacitor C1, the capacitance of which is 100 PF (picofarad).
It is an object of the present invention to provide a semiconductor device that may be driven stably even if the increase in speed of the supply voltage changes.
It is another object of the present invention to provide a semiconductor device that may be driven by low current.
It is another object of the present invention to provide a semiconductor device that may be driven by low voltage.
It is further object of the present invention to provide a semiconductor device that may be driven at fast speed.
According to one aspect of the present invention, for achieving the above object, there is provided a semiconductor device, with a first node which has a first voltage; a second node which has a second voltage, wherein the second voltage is lower than the first voltage; a first current mirror circuit which has an input terminal and an output terminal, wherein the first current mirror circuit is coupled with the first node; a second current mirror circuit which has an input terminal and an output terminal, wherein the input terminal of the second current mirror circuit is coupled with the output terminal of the first current mirror circuit, wherein the output terminal of the second current mirror circuit is coupled with said input terminal of the first current mirror circuit and wherein the second current mirror circuit is coupled with said second node; and a start-up circuit which comprises a third node, a first switch which electrically connects the first node and the input terminal of the second mirror circuit based on a voltage level at the third node, a second switch which electrically connects the first node and the third node based on a voltage level at the input terminal of the first current mirror circuit, and a third switch which electrically connects the first node and the third node based on an inverted voltage of the voltage level at the third node.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.